THERMIONIC-FIELD EMISSION IN AIGaAs/GaAs 1WO-DIMENSIONAL ELECTRON GAS CHARGE-COUPLED DEVICES

Dark current in AIGaAs/GaAs two-dimensional electron gas charge-coupled devices (2DEG CCDs) is investigated both theoretically and experimentally. Measurement of the dark current for temperatures in the range 160 K to 360 K was performed and compared with the results of numerical modelling. It is found that thermionic-field emission of electrons from the gate to the channel is the dominant mechanism in uniformly-doped and planar-doped device structures. Good agreement between theory and experiment was obtained. Metal-semiconductor field-effect transistor (MESFET)-type GaAs charge-coupled devices (GGOs) have demonstrated high charge transfer efficiency (GTE) at frequencies exceeding 1 GHz and are applicable to very high speed analog signal processing'. With the advent of new infrared detectors built from III-V materials by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVOl, the potential integrability of the detector and III-V based CCOs has motivated the investigation of GaAs and related heterostructure GCOs for monolithic imaging detector array readout applications. Two­ dimensional electron gas (20EG) CCDs, an emerging technology, are expected to have several advantages over MESFET-type GaAs CCDs: a higher electron mobility at low electric field and temperature, a larger charge handling capacity, a low insertion loss, a reduced clock swing, and a fabrication compatibility with high speed, low noise 2DEG field-effect transistors (FETs) for output amplifiers and supporting digital circuitry. Recently, the first resistive-gate (20EG) CGD on a uniform-doped Alo3Gao.7As/GaAs heterostructure was reported 3 , and demonstrated high charge transfer efficiency (CTE of 0.9990) for clock frequencies between 13 MHz and 1 GHz at room temperature. Degradation of CTE and reduction of the output signal amplitude were observed for lower frequencies (for example, CTE of 0.98 at 1.5 MHz clock frequency), due to the anomalous accumulation of carriers in the CCO well, referred to as dark current. A thermally activated gate leakage current was believed to be the origin of the dark current since the CTE was improved by cooling the device and subsequent measurement of the gate leakage current showed that the total accumulation of the gate leakage current in the CCO potential well during the period of charge transfer was consistent with the maximum well capacity. 2 Extension of the low frequency operating range of the 20EG CCO , which is directly related to the dark current, is important for infrared imaging detector array readout applications to allow long integration periods at low temperature, nominally 65 K. An understanding and reduction of dark current is also important for 2DEG-based dynamic memory devices and circuits. In this paper, reduction of the gate leakage current by more than two orders of magnitude through the use of a planar-doped structure is reported. The physical mechanism responsible for the dark current is shown to be thermionic field emission. The material structure of the 2DEG CCO consists of, from bottom to top, a semi-insulating GaAs substrate, a GaAs/AIGaAs superlattice buffer, an 8000 A thick undoped GaAs layer, a 30 A thick undoped AIGaAs spacer layer, a planar-doped AIGaAs layer (4.5x10 12 Si atoms/cm\ a 350 A thick undoped AIGaAs layer, and a 300 A thick GaAs cap layer doped with 4x10/cm 3 Si atoms. After a 4000 A deep mesa etch, AuGe ohmic contacts were formed and annealed at 425 C for 45 sec under a forming gas am­ bient. Using the AuGe ohmic pattern as a mask, the 300 A GaAs cap layer and 100 A of the AIGaAs layer were etched with a 1:1 :1000, NH 40H:H 20 2 :H 20 solution. A resistive layer (cermet) was e-beam evaporated on the CCO channel with an equal weight mixture of Cr and SiO powder sources , forming a Schottky contact to the underlying AIGaAs layer. The resistive layer was 3000 A thick with a sheet resistance of 250 kn/o. The first Cr and Au metallization was done bye-beam and thermal evaporations, respectively, to form finger electrodes on the resistive layer and gate electrodes for the output amplifier. The second Cr/ Au metallization was used to connect finger electrodes with the same phase (using a 3500A thick SiD as an inter-layer dielectric). The CCO delay line is composed of 32 stages with a four-phase clocking scheme 3 (128 electrodes). The finger electrodes are 1pm long, 100 pm wide and spaced by 4 pm. A source-follower (1 pm long, 100 pm wide gate) with the same size on-chip load and a dual-gate reset FEr were used to read out the signal from the CCO channel. Before operating the CCO delay line, basic device characterization was performed. The pinch-off voltage and transconductance of a 1 pm gate FEr were -1 V and 100 mS/rnm, respectively. The gate leakage current of the planar-doped structure was measured to be more than two orders of magnitUde lower than that of a uniform-doped structure at room temperature. The CTE of this device is plotted in Fig. 1 in comparison with that of the uniform-doped ceo, which shows an extended low frequency limit by a similar factor as the gate leakage reduction. (Note that the test station limit was 1GHz.) The eTE was evaluated using the method of Brodersen, et a1. . To understand the low frequency limit of this device, various mechanisms of gate leakage current were considered and analyzed. It should be noted that in the depletion­ mode CCO, electron transport from gate to channel is of concern, whereas in typical enhancement-mode 20EG FETs, transport from channel to gate dominates gate leakage current. Calculation of thermionic emission (TE) current predicted current levels much lower than experimentally seen, so that other mechanisms such as thermionic-field emission (TFE)6 or impurity-assisted tunneling were considered. In order to resolve the mechanisms, a numerical calculation was performed to calculate the TFE current. Since the gate leakage current of the eco channel reaches a saturated maximum when the potential well is empty of signal charge, the modelled structure was assumed to be reverse-biased beyond the pinch-off voltage with the barrier shape shown in Fig. 2. The effective barrier is reduced by increased surface electric field leading to a qualitative understanding as to why the planar-doped structure, with lower surface electric field, has -4 lower gate leakage current compared to the uniform-doped structure. The tunneling probability for the barrier using the WKB approximation is, -41T T(Ez) = exp{ h (1)